A digital signal processor (DSP) providing improved performance, reduced code size, more on-chip memory and high bandwidth integrated peripherals, including Serial RapidIO bus for inter-processor communications, has been developed by Texas Instruments Inc. (TI), Dallas TX.
According to TI, developers of telecommunications, network and video infrastructure end equipment and high-end imaging systems using the TMS320C6455 will see system performance gains resulting from 2x to 12x boosts in device performance and I/O bandwidth.
This will allow them to integrate more high-bandwidth channels, achieve higher image definition, and produce more efficient software easily, for faster time-to-market.
“As the telecom, imaging, networking and video industries continue to develop new services, the C6455 DSP’s programming flexibility allows developers to keep pace with changes in standards and to quickly implement multiple voice and video codecs in their system designs,” Thomas Brooks, TI DSP platform marketing manager, says.
100-percent code compatible with previous TMS320C64x devices, the new chip incorporates:
*Serial RapidIO, providing up to 25Gbit/s interconnectivity, enabling high performance multi-processing that is 12 times faster than previous external memory interfaces.
*Gigabit Ethernet MAC (Memory Access Controller), providing 10 times more Ethernet bandwidth than previous C64x devices.
*DDR2 (Double Data Rate) external memory interface delivering twice the throughput of currently available devices.
*66MHz PCI (Peripheral Component Interconnect) bus interface, providing twice the frequency of previous processors.
*2MBytes of L2 memory, twice the amount as previous C64x devices.
The integrated industry-standard Serial RapidIO bus decreases overall system cost by reducing the need for additional devices used for switching and processor aggregation. Supported by an industry association of leading device, system and software manufacturers, the interconnect enables high-speed, packet-switched peer-to-peer connectivity.
This makes it much easier to implement multi-processing, providing a performance breakthrough for multi-channel implementations on multiple processors, TI says.
For video infrastructure applications, a 1x link is fast enough to send high-definition (HD) 1080i raw video between devices and a 4x link can easily send HD 1080p raw video between devices with bandwidth to spare.
The enhanced DSP core adds new specialized instructions that, on average, make code 20 to 30 percent more compact and 20 percent more cycle efficient than code based on the current C64x DSP architecture, TI says.
The new instructions include complex and 32-bit-wide multiplications and simultaneous add/subtract instructions, increasing Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT) performance.
The core can execute eight 16×16 multiply and accumulate instructions per cycle, twice as many as the current C64x DSP core. Since the new instruction set is a superset of current C64x instructions, software for the new device is 100 percent object code compatible with code for existing C64x DSPs.
