 A second-generation virtual digital signal processing (DSP) design lab which builds upon the Spartan-3 two-million-gate XC3S2000 FPGA from Xilinx Inc., has been developed by advanced technology active components and systems distributor Nu Horizons Electronics Corp. (a collaborative effort with a number of industry players, including Xilinx, LT, Intersil and The Mathworks).
The virtual lab is the first of its kind to incorporate The Mathworks Simulink simulation and model-based design with both analog-to-digital (A/D) converter interfaces and digital-to-analog (D/A) converter modules, Nu Horizons says. In addition, the lab offers test equipment to provide signal insertion and measure output waveforms.
The lab is configured to allow users to create and download high performance DSP applications. Advanced algorithms can be developed and complex measurements performed via a full complement of test equipment connected to the virtual lab environment.
Both a signal/pattern generator and high speed oscilloscope connect to A/D and D/A modules and each piece of test equipment is placed in the host mode for users to remotely manage the equipment’s front panel controls. Settings and scripts are also easily saved for re-use on future sessions, while signal insertion output measurement capability enables designers to validate their algorithms.
Reference DSP designs are provided, allowing design engineers to evaluate the Spartan-3 2000 FPGA in a pre-verified environment. The lab package consists of three reference labs:
*SysGen Tutorial - lab introducing customers to other important design features, including ChipScope, HDL Cosim, Hardware Cosim and PicoBlaze.
*FFT with 256 Tap FIR filter and interpolation by 3 - lab offering ease of use and reasonably high performance allowing design engineers to evaluate tool interfaces as well as hardware. The filter design is provided to the design engineer using the FDA Tool to generate coefficients, offering the designer the ability to modify coefficients and view results. Simulation can be run in Sysgen, as well as run live in hardware.
*Equalized 16-QAM demodulator including the adaptive filter - receiver architecture provides subsystems demonstrating adaptive channel equalization and carrier tracking on a random QAM data source.
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