A new transistor architecture that overcomes many of the design and manufacturing challenges associated with vertical multi-gate devices was recently demonstrated by Freescale Semiconductor Inc., Austin TX, at the IEEE International Electron Devices Meeting (IEDM 2005) in Washington DC.
The inverted T-channel field-effect transistor (ITFET) device has the industry’s first combination of vertical and planar thin body structures within a single transistor, Freescale says, and points to a new breed of dramatically smaller, higher performing semiconductors that require less power.
According to the firm, traditional CMOS devices deploy transistors onto the surface of the silicon in a planar or horizontal fashion. In recent years new device architectures have emerged, featuring vertical transistors that utilize multiple sides of the silicon.
Vertical transistors are appealing in part because they reduce leakage and provide higher drive current, functions of having more than one gate to control the device. Multiple gates pack more computing power into less space and reduce power consumption.
But vertical transistors present fundamental design and manufacturing challenges related to mechanically stability, sub-lithographic feature sizes and patterning over tall topographies.
By combining the stability and manufacturability of planar devices with the low leakage and other benefits of vertical devices, Freescale says ITFET bridges the debate on planar versus vertical CMOS devices and offers key advantages of both technologies in a single device.
“Only five years ago, the prevailing consensus of the industry held that vertical devices were impractical,” Freescale Chief Technology Officer Claudine Simson says. “Due to Freescale’s uncompromising commitment to technology innovation and manufacturing know-how, many vertical device issues that once were considered insurmountable have now been resolved.”
“ITFET represents one of the most innovative and potentially disruptive semiconductor manufacturing advancements since the industry standardized on traditional planar CMOS technology more than 20 years ago,” Simson adds.
ITFET offers better manufacturability than FinFET transistors and other vertical devices. It also provides significant advantages over planar thin body devices and other vertical multi-gate designs, including lower current leakage, easier transistor width proportioning, lower parasitic capacitance and increased on-current.
The vertical and planar regions of the ITFET couple to provide enhanced current capability from an increased channel width without increasing chip area. The architecture incorporates silicon in the planar regions below the vertical channels, improving manufacturability by reducing undercut below the vertical channels, reducing parasitic resistance and enhancing the mechanical stability of the vertical channels.
The ITFET device was fabricated using innovative process techniques on 90-nanometer (nm) CMOS silicon-on-insulator production equipment at Freescale’s Austin Technology & Manufacturing Center. The firm plans to incorporate the technology in a range of high-end devices beginning at the 45nm node and beyond.
