The Fusion Programmable System Chip (PSC) device line now being shipped by programmable logic manufacturer Actel Corp., Mountain View CA, is claimed by its maker to be the world’s first mixed-signal FPGA family. By integrating mixed-signal analog, flash memory and FPGA fabric in a monolithic device, it enables designers to quickly move from concept to completed design and deliver feature-rich systems to market, Actel says.
It brings the benefits of programmable logic to application areas such as power management, smart battery charging, clock generation and management and motor control that until now have only been served by either costly and space-consuming discrete analog components or mixed-signal ASICs.
Usable in conjunction with ARM7 and 8051-based soft MCU cores, the new ICs allow designers to integrate a wide range of functionality into a single device while at the same time offering the flexibility of upgrades in the field or deep in the production cycle.
“With the Actel Fusion PSC we are removing the handcuffs from system architects and allowing them to focus on adding unique features and enhancing end-product value,” Actel President and CEO John East says. “Designers will be able to treat the Fusion PSCs like a mixed-signal ASIC without all the ASIC penalties of long design cycles and high costs.”
The devices integrate a configurable 12-bit successive approximation register (SAR) analog to digital converter (ADC) operating to to 600kSps. The flexible analog block supports MOSFET gate driver output and multiple analog inputs from -12 to +12 volts with optional prescaler, enabling direct connection and control of a wide variety of analog signals.
According to Actel, the family is the only programmable logic line to include embedded flash memory, up to 1Mbyte per device, providing 60ns random access and 100MHz access in read-ahead mode. The flash uses a user-configurable data bus supporting x8, x16 and x32 bit widths and provides error correction circuitry (ECC) with single-bit error fix and two-bit error-detect capabilities.
Pseudo EEPROM can be achieved with endurance extender IP. Users can easily reconfigure analog block settings to perform widely different functions by simply downloading data from embedded flash.
Ultra low-power sleep and stand-by modes handle Level 0 LAPU system supervisory activities, such as system board power-up sequencing and configuration.
To support the devices a new comprehensive design environment includes software tools, intellectual property (IP) and reference designs.
