A 45-nanometer (45nm) semiconductor manufacturing process that leverages a wet lithography process to double the number of chips produced on each wafer, increase processing performance and reduce power consumption has been developed by Texas Instruments Inc. (TI), Dallas TX.
Through the use of numerous proprietary techniques TI says it will drive the capabilities of its multi-million transistor, system-on-chip (SoC) processors to new levels, increasing performance by 30 percent while reducing power consumption 40 percent.
TI estimates that its 45nm process and SoC integration capabilities will mean users can get up to a 30 percent improvement in device speed, which can translate to more video frames per second for a better user experience on mobile phones. In addition, wireless users will be able to run more simultaneous applications such as a game with 3-D graphics in parallel to a video conference between the players, with e-mail synchronizing in the background.
TI says that other projections show its 45nm SoCs will reduce power by 40 percent, allowing longer video playback time and up to 30 percent longer cell phone stand-by time.
The convergence of communications and computing on mobile devices, and the growing use of high performance multimedia, gaming and productivity applications, has pushed lower power consumption to the forefront of semiconductor technology advancement, the chip maker says.
Its new process leverages SmartReflex power and performance management technologies that combine intelligent and adaptive silicon, circuit design, and software. TI says it takes a system-level approach with SmartReflex technologies to extend the capability across an entire 45nm SoC design, including adaptive hardware and software technologies that dynamically control voltage, frequency and power based on device activity, modes of operation and process and temperature variation.
The new process also supports DRP architecture to integrate digital RF functionality in single-chip wireless devices. TI says this SoC approach to wireless transmit and receive functions allows it to apply its highly efficient CMOS manufacturing infrastructure to reduce overall system cost, reduce power consumption and free up board space.
Other integration options in the 45nm design libraries include a host of analog components such as resistors, inductors and capacitors that allow further SoC integration of formerly stand-alone functions.
For the first time, the firm will implement the use of 193nm immersion photo-lithography to accomplish density improvements that competitors using dry lithography at 45nm are unable to achieve. The use of 193nm immersion tools delivers the higher resolution and corresponding smaller device features needed to maximize the benefits of migrating to a new process, TI says.
193nm immersion tools work by placing a thin layer of liquid between the lens and the wafer to ease the process of transferring smaller circuit designs.
The company says its work in this area has resulted in the development of what it believes to be the smallest 45nm SRAM memory cell, occupying only 0.24 square microns, up to 30 percent smaller than other 45nm memory cell devices announced to date.
Memory cells are often the first development vehicle for new manufacturing technologies and provide valuable data about transistor densities that will be achieved on complete SoCs, TI says.
Other improvements in how many transistors TI’s 45nm process can support on a chip are attributed by TI to the use of an ultra low-k dielectric that achieves a k value of 2.5, and reduces interconnect capacitance by 10 percent.
TI says this will be its third-generation process technology to use low k dielectrics for reducing capacitance and propagation delays within a device’s interconnect layers, and boosting chip performance.
